This invention relates to an integrated circuit for writing, reading and erasing memory matrices employing insulated-gate field-effect transistors having a non-volatile storage behavoir. Such memory matrices may consist of field-effect transistors such as MNOS transistors whose gate insulating layer is composed of two different materials, e.g., silicon dioxide and silicon nitride. Another group of such memory matrices employs so-called "floating-gate" transistors which comprise a gate electrode which has no electrical connection to the outside.
One group of "floating gate" transistors is described in "1980 IEEE International Solid-State Circuits Conference, Digest of Technical Papers", February 1980, pp. 152, 153 and 271, and "Electronics", Feb. 28, 1980, pp. 113 through 117. The characteristic feature of this kind of floating gate transistors is that they operate with a pure tunneling effect without involving hot charge carriers. For the purposes of the present specification, memory cells employing these conventional types of floating gate transistors are referred to as TUSIS memory cells, with the acronym standing for the English name Tunnel Single Injector Storage Cell.
Another variant form of floating gate transistors making use of the tunneling effect is disclosed in the earlier European Patent Application 81 10 1105.5 which is based on the German Patent Application P 30 07 892.3-53. For the purposes of the present specification, this variant form is referred to as TITEF memory cells, with the acronym standing for Tunnel-Injector Tunnel-Emitter, Floating-Gate.
To operate such memory matrices having a non-volatile storage behavior requires circuits for writing, reading and erasing, which are also referred to as peripheral circuits. The circuits previously employed for this purpose were MOS insulated-gate field-effect transistor circuits, realized in a single-channel technique, i.e., employing transistors of a single channel conductivity type. In the inoperative state of such single-channel circuits, a quiescent current always flows. Therefore, the current requirement of the total circuit including the memory matrix and the peripheral circuit increases as the memory size increases to an extent that the realization of the total circuit is not practical.
Although the aforementioned TUSIS or TITEF memory cells require only negligibly small currents for programming, this advantage is not noticeable because the previous conventional peripheral circuits have considerable current consumption.